Methods and Tools for the Analysis, Verification and Synthesis of Genetic Logic Circuits
(Year 2014 - present)
Genetic logic circuits are an application of synthetic biology, where parts of the DNA of a living cell are engineered to perform a dedicated Boolean function triggered by appropriate concentration levels of certain proteins or other species. These logic circuits work similar to electronic logic circuits, but are much more stochastic and hence much harder to characterize. Simulation and behavioral analysis of genetic circuits is a standard approach of functional verification prior to their physical implementation. This research work contributes in the field of bio-design automation (BDA) by introducing new tools and methods for the analysis, verification, synthesis and technology mapping of genetic logic circuits.
A user-friendly software tool named D-VASim (Dynamic Virtual Analyzer and Simulator) is introduced, which provides a virtual laboratory environment to simulate and analyze the behavior of genetic logic circuit models represented in an SBML (Systems Biology Markup Language). Hence, SBML models developed in other software environments can be analyzed and simulated in D-VASim. D-VASim offers deterministic as well as stochastic simulation; and differs from other software tools by being able to extract and validate the Boolean logic from the SBML model. D-VASim is also capable of analyzing the threshold value and propagation delay of a genetic circuit model.
Another tool named, GeneTech, is developed which allows user to optimize, synthesis and perform Technology mapping of Genetic logic circuits using the genetic gates library (developed at MIT).
Tool's Availability: D-VASim is available to download for MAC and Windows OS from bda.compute.dtu.dk/downloads.
A video briefly describing the motivation to develop D-VASim.
For better resolution, please watch it on youtube.
A brief demonstration of genetic circuit model simulation in D-VASim.
For better resolution, please watch it on youtube.
The mitigation of single-event upsets (SEUs) through modular or functional redundancy is a traditional approach for designing fault-tolerant systems; however, even in multiple redundant systems, SEUs can lead to a system failure if they occur simultaneously. Previous fault-tolerant approaches have proposed run-time reconfiguration to regain the lost functionality. We worked with a similar strategy to overcome failures caused by unidirectional SEUs occurring simultaneously in both frontline and redundant modules, but the approach proposed in this work not only improves reliability but also requires low-overhead as compared to previous methodologies. The proposed architecture is an array of computation tiles containing computation cells and corresponding hot-spares. Each computation tile has a separate region for spare cells. The simultaneous faults are handled by an on-chip fault-tolerant core and external host software that partially reconfigure the spare-cells region of a computation tile. The proposed architecture is implemented on a Xilinx Virtex-5 FPGA device and verified with the aid of simple digital application. Compared to previous schemes, our approach requires up to 9.6x less area overhead while providing 57.6% more reliability to mask multiple unidirectional SEUs.
A Self-Repairing Bio-Inspired Fault-Tolerant FPGA Architecture
The system should have fault-tolerant and self-repairing capabilities in order to make sure that it is working properly in any hostile environment where its functionality can seriously be affected by the radiations present in the environment. In this research, I developed a complete homogenous fault-tolerant FPGA architecture with self-repairing capabilities. Unlike previously proposed architectures, the present one can not only be implemented on the existing island-style FPGA architecture but can also be able to fabricate entirely as a new device utilizing the existing routing network strategies. The developed architecture is unique in a way that it is able to heal transient (unidirectional bit flip errors) and permanent (uni-directional) stuck-at faults, at LUT level, all at the same time. A fault-tolerant core is developed to handle on-chip permanent errors with the collaboration of off-chip external PC software.
Project demonstration videos are shown below:
1. Brief introduction to software.
2. Full project demonstration.
This project is the enhancement of work presented in "Implementation of SCADA System for Unsought Tablets Detection through Morphological Image Processing, Proceedings of the 12th IEEE International Multi-topic Conference, ISBN: 978-1-4244-2823-6, pp. 493-500".
The purpose of this project is to speed-up the system process via implementing the image processing part of above referenced project on GPU and CPU both. A 44.94x speed improvement in CPU-GPU algorithm as compare to CPU-only version was determined. Then GPU algorithm was further optimized to reduce global memory traffic and a 9.76x additional improvement in speed of processing the image was observed. Overall GPU-CPU algorithm runs 54.9x faster than a CPU-only algorithm.
A Novel Automated Experimental Approach for the Measurement of On-Chip Speed Variations through Dynamic Partial Reconfiguration
In this research, a complete automated experimental setup for the measurement of on-chip delay variations through dynamic partial reconfiguration was developed. The experiment was performed on two same Virtex-5 (XC5VLX110T) devices on the basis of which intra-die and inter-die speed comparisons were made. On-chip sensor map was developed, consists of 60 sensors out of which only alternating sensors remains active at a time. This is done to avoid neighboring sensors heat dissipation. Host GUI was developed on LabVIEW platform which monitors and supervises the whole process running on chip. GUI allows user to load partial bitstream of any sensor map. While maintaining the sensor topology constant, we found the intra-die speed variations up to 6-10%. However, inter-die speed comparison result depicts that one chip is 2-10% faster than another one.
Development and Verification of Soft IP Core of USB 3.0 Device in Verilog HDL
It was my Final Year Project (B.E. Thesis) and was completed under the supervision of EONSIL, Austin TX, 78730. In this research I, together with my group mates, developed a complete synthesizable RTL of SuperSpeed USB 3.0 device on Verilog HDL. I contributed in this project by developing the Physical (MAC) layer of USB 3.0 device and the Master Controller.
Development of Solid State Drive and Embedded Data Storage Applications
I was called upon (in early 2008) by the CEO of EONSIL.LLC, a hardware designing company situated in Austin, TX, to work on Embedded Data Storage Applications for them. I was assigned a task to design the Dual Channel Solid State Drive. I accomplished my assigned task successfully and gained a lot of knowledge while working with them as it was my first experience to work with professionals.
Implementation of SCADA System for Unsought Tablets Detection through Morphological Image Processing (Year 2008)
The project was designed to provide an optimum solution and proficient algorithm to pharmaceutical industries in order to detect and remove defective tablets through an automated process.
GSM Based Security System using LabVIEW
The cost effective security system which could be installed at the possible entrances of homes, offices, highly secured places etc. The designed system informs the interruption by making a call to a user's mobile phone. Thus the user gets informed that someone has got passed through the entrance. Moreover, the system was intelligent enough to communicate with the user through an SMS i.e. the user can instruct the system to perform predefined tasks.
I was highly praised by my project advisor on this effort. I wrote a paper on it and it was an honored for me to became a first student (while in second year of engineering) of my batch whose research paper, GSM based Security System using LabVIEW, got published in the First International Conference on Computer, Control and Communication, Pakistan Naval Engineering College (PNEC) Karachi, November 12-13, 2007.
Low Cost Fabrication of Highly Reliable Single-sided PCBs
I established a Printed Circuit Boards (PCBs) lab at my home where I was able to designed and fabricate professional single-sided PCBs. This was the first time I initiated some thing that brought me to the peak of self-confidence that I can do anything else I am determined to do. This experience of designing and fabricating PCBs led me to enter in our department's PCB lab where I was honored to facilitate the newly employed technician of PCB Lab and worked on highly efficient and costly machines of fabricating double-sided printed circuit boards. I conducted two workshops on the fabrication of single and double sided PCBs in which I discussed the issues of perfect designing of PCBs and shared my practical experience of working in my home-made lab.