Cloud-COPASI is a web-based tool for running computationally intensive simulation and analysis tasks in parallel on a high-throughput computing pool. Cloud-COPASI can connect to existing computing pools, or provides a simple interface for launching a new computing pool using the Amazon Elastic Compute Cloud (EC2).

Circuit Construction in GeneTech with Enhanced SBOL support

Integration of additional features in GeneTech software tool including the support of SBOL export with DNA basepair generation; drag-drop functionality for creating genetic circuits using logic gates. The entire GeneTech was also transformed into Python.

A Parallel Approach to Perform Threshold Value Analysis and Verification of Genetic Logic Circuit Models

In this work a parallel implementation of the threshold value analysis algorithm (in DVASim) has been proposed which produces the results faster by up to 16 times.


GeneTech (extracted from Genetic Technology mapping) is a tool which allows a user to generate genetic logic circuits only by specifying the logical function desired to be achieved in a living cell. It does not require a user (either biologist or a computer scientist) to learn any programming language.


A user-friendly software tool named DVASim (Dynamic Virtual Analyzer and Simulator) is introduced, which provides a virtual laboratory environment to simulate and analyze the behavior of genetic logic circuit models represented in an SBML (Systems Biology Markup Language).

Design and Implementation of a Fault-Tolerant RISC-V Processor Architecture on FPGA

This project goal was to implement a subset of RISC-V processor on FPGA and make it fault-tolerant.

A Self-Repairing Bio-Inspired Fault-Tolerant FPGA Architecture

A fault-tolerant FPGA architecture is developed which not only improves reliability but also requires low-overhead as compared to previous methodologies.

Performance Evaluation of CPU-GPU and CPU-only Algorithms for Detecting Defective Tablets through Morphological Imaging Techniques

This project is the enhancement of the image processing algorithm presented in our previous work on GPUs and its comparison with CPU-only version.

A Novel Automated Experimental Approach for the Measurement of On-Chip Speed Variations through Dynamic Partial Reconfiguration

In this research, a complete automated experimental setup for the measurement of on-chip delay variations through dynamic partial reconfiguration was developed. The experiment was performed on two same Virtex-5 (XC5VLX110T) devices on the basis of which intra-die and inter-die speed comparisons were made.

Development and Verification of Soft IP Core of USB 3.0 Device in Verilog HDL"

In this project I, together with my group mates, developed a complete synthesizable RTL of SuperSpeed USB 3.0 device on Verilog HDL.