Cloud COPASI: A software tool for Biochemical Simulation and Analysis using Cloud Computing
(Year 2020 - )
Cloud-COPASI can run a number of simulation and analysis tasks, including global sensitivity analyses, stochastic simulations, parameter scans, optimizations, and parameter fitting. Each task is automatically slit into a number of smaller jobs, which are executed in parallel, allowing for significant speed-ups in running time.
Models must be prepared using the desktop version of COPASI (COmplex PAthway SImulator), a widely used free, open-source, cross-platform simulation tool.
Executable: The online link will be available soon.
Source: Can be accessed at https://github.com/copasi/cloud-copasi
Generating detailed SBOL representation of genetic logic circuits along with improved designing capability, and SBML export in GeneTech
Integration of additional features in GeneTech software tool including the support of SBOL export with DNA basepair generation; drag-drop functionality for creating genetic circuits using logic gates. The entire GeneTech was also transformed into Python.
This project was supported by Google under "Google Summer of Code" program.
A Parallel Approach to Perform Threshold Value Analysis and Verification of Genetic Logic Circuit Models
In this work a parallel implementation of the threshold value analysis algorithm (in DVASim) has been proposed which produces the results faster by up to 16 times. The algorithm was further improved for consistent runtimes across multiple simulation runs under the same parameter settings, reducing the worst-case standard deviation in runtime from 6.637 to 1.841. New algorithm also estimates the threshold value more accurately.
GeneTech (extracted from Genetic Technology mapping) is a tool which allows a user to generate genetic logic circuits only by specifying the logical function desired to be achieved in a living cell. It does not require a user (either biologist or a computer scientist) to learn any programming language.
The tool first performs logic optimization, followed by synthesis and technology mapping using a library of genetic logic gates. In the end, GeneTech performs technology mapping to generate all the feasible circuits, with different genetic gates, to achieve the desired logical behavior.
A user-friendly software tool named DVASim (Dynamic Virtual Analyzer and Simulator) is introduced, which provides a virtual laboratory environment to simulate and analyze the behavior of genetic logic circuit models represented in an SBML (Systems Biology Markup Language). Hence, SBML models developed in other software environments can be analyzed and simulated in D-VASim. D-VASim offers deterministic as well as stochastic simulation; and differs from other software tools by being able to extract and validate the Boolean logic from the SBML model. D-VASim is also capable of analyzing the threshold value and propagation delay of a genetic circuit model.
A video briefly describing the motivation to develop D-VASim.
For better resolution, please watch it on youtube.
A brief demonstration of genetic circuit model simulation in D-VASim.
For better resolution, please watch it on youtube.
Design and Implementation of a Fault-Tolerant RISC-V Processor Architecture on FPGA
This project goal was to implement a subset of RISC-V processor on FPGA and make it fault-tolerant.
Role: BE Thesis Supervisor
Tools and skills used: Xilinx ZEDboard, ARM processor, FPGA, XILINX Vivado, ModelSim, Verilog HDL
A Self-Repairing Bio-Inspired Fault-Tolerant FPGA Architecture
The mitigation of single-event upsets (SEUs) through modular or functional redundancy is a traditional approach for designing fault-tolerant systems; however, even in multiple redundant systems, SEUs can lead to a system failure if they occur simultaneously. Previous fault-tolerant approaches have proposed run-time reconfiguration to regain the lost functionality. We worked with a similar strategy to overcome failures caused by unidirectional SEUs occurring simultaneously in both frontline and redundant modules, but the approach proposed in this work not only improves reliability but also requires low-overhead as compared to previous methodologies. The proposed architecture is an array of computation tiles containing computation cells and corresponding hot-spares. Each computation tile has a separate region for spare cells. The simultaneous faults are handled by an on-chip fault-tolerant core and external host software that partially reconfigure the spare-cells region of a computation tile. The proposed architecture is implemented on a Xilinx Virtex-5 FPGA device and verified with the aid of simple digital application. Compared to previous schemes, our approach requires up to 9.6x less area overhead while providing 57.6% more reliability to mask multiple unidirectional SEUs.
Role: Research Assistant, Sole Developer/Designer
Tools and skills used: Xilinx Virtex-5 FPGA, Xilinx ISE Toolchain, Verilog HDL, ModelSim, LabVIEW
Project demonstration videos are shown below:
1. Brief introduction to software.
2. Full project demonstration.
This project is the enhancement of the work presented in "Implementation of SCADA System for Unsought Tablets Detection through Morphological Image Processing, Proceedings of the 12th IEEE International Multi-topic Conference, ISBN: 978-1-4244-2823-6, pp. 493-500".
The purpose of this project is to speed-up the system process via implementing the image processing part of above referenced project on GPU and CPU both. A 44.94x speed improvement in CPU-GPU algorithm as compare to CPU-only version was determined. Then GPU algorithm was further optimized to reduce global memory traffic and a 9.76x additional improvement in speed of processing the image was observed. Overall GPU-CPU algorithm runs 54.9x faster than a CPU-only algorithm.
Role: MS student, Sole Developer
Tools and skills used: NVIDIA GPUs, CUDA C, C++, Visual Studio
A Novel Automated Experimental Approach for the Measurement of On-Chip Speed Variations through Dynamic Partial Reconfiguration
In this research, a complete automated experimental setup for the measurement of on-chip delay variations through dynamic partial reconfiguration was developed. The experiment was performed on two same Virtex-5 (XC5VLX110T) devices on the basis of which intra-die and inter-die speed comparisons were made. On-chip sensor map was developed, consists of 60 sensors out of which only alternating sensors remains active at a time. This is done to avoid neighboring sensors heat dissipation. Host GUI was developed on LabVIEW platform which monitors and supervises the whole process running on chip. GUI allows user to load partial bitstream of any sensor map. While maintaining the sensor topology constant, we found the intra-die speed variations up to 6-10%. However, inter-die speed comparison result depicts that one chip is 2-10% faster than another one.
Role: MS student, Sole Developer
Tools and skills used: Xilinx Virtex-5 FPGA, Microblaze microprocessor, Xilinx ISE Toolchain, ModelSim, Verilog HDL
Development and Verification of Soft IP Core of USB 3.0 Device in Verilog HDL
It was my Final Year Project (B.E. Thesis) and was completed under the supervision of EONSIL, Austin TX. In this research I, together with my group mates, developed a complete synthesizable RTL of SuperSpeed USB 3.0 device on Verilog HDL. I contributed in this project by developing the Physical (MAC) layer of USB 3.0 device and the Master Controller.
Role: BE Thesis student, Co-Developer
Tools and skills used: ModelSim, Verilog HDL
Development of Solid State Drive and Embedded Data Storage Applications
Designing and development of a dual-channel NAND flash data storage device for a company named EONSIL LLC, a hardware designing company for embedded data storage applications located in Austin, TX.
Role: Intern, Consultant
Tools and skills used: Circuit Designing, OrCAD Schematic, OrCAD PCB Designing, PCB Fabrication.
Implementation of SCADA System for Unsought Tablets Detection through Morphological Image Processing (Year 2008)
The project was designed to provide an optimum solution and proficient algorithm to pharmaceutical industries in order to detect and remove defective tablets through an automated process.
This was a group project of four students. I contributed in the development of Image processing algorithm to detect the defective tablets. I also developed an HMI (Human Machine Interface) to control the entire physical system using a graphical user interface.
Role: Third year undergrad student
Tools and skills used: Circuit Designing, MATLAB, Image processing, SCADA, LabVIEW, Hardware interfacing
GSM Based Security System using LabVIEW
The cost effective security system which could be installed at possible entrances of homes, offices, highly secured places etc. The designed system informs the interruption by making a call to a user's mobile phone. Thus, a user gets informed that someone has intrude and break into a secured area. Moreover, the system was intelligent enough to communicate with the user through an SMS i.e. the user can instruct the system to perform predefined tasks.
I was highly praised by my project advisor on this effort. I wrote a paper on it and it was an honored for me to became a first student (while in second year of engineering) of my batch whose research paper, GSM based Security System using LabVIEW, got published in the First International Conference on Computer, Control and Communication, Pakistan Naval Engineering College (PNEC) Karachi, November 12-13, 2007.
Role: Second year undergrad student
Tools and skills used: Circuit Designing, LabVIEW, Hardware interfacing
Low Cost Fabrication of Highly Reliable Single-sided PCBs
I established a Printed Circuit Boards (PCBs) lab at my home where I was able to design and fabricate professional single-sided PCBs. This was the first time when I initiated something that brought me to the peak of self-confidence that I can do anything else I am determined to do. This experience of designing and fabricating PCBs led me to enter in our department's PCB lab where I was honored to facilitate the newly employed technician of PCB Lab and worked on highly efficient and costly machines of fabricating double-sided printed circuit boards. I conducted two workshops on the fabrication of single and double sided PCBs in which I discussed the issues of fault-free designing of PCBs and shared my practical experience of working in my home-made lab. I also wrote an article to disseminate my work in the annual departmental magazine named SPARK.
Role: First year undergrad student
Tools and skills used: Circuit Designing, OrCAD Schematic, OrCAD PCB designing, PCB Fabrication, Photo-plotting, Screen-printing.