Institute: Habib University
Offered in: Fall 2018, Spring 2019
These labs are designed to help students develop a RISC-V processor (with reduced instruction set) throughout the semester.
The exercises have been designed to get the students acquainted with the hardware design skills. Students learn how to design hardware using hardware description language (HDL); how to simulate an HDL design; and how to test it on a reconfigurable chip. After getting familiar with the design flow, students are required to develop processor peripherals. This give them a better idea of how different modules work in Single Cycle RISC processor and Pipelined RISC processor. Thus the knowledge gained in theory classes are reinforced.
I also developed a software tool for students to observe on-chip data on a computer screen. The software (windows installer) can be downloaded using the link shown above.