Fast Threshold Value Analysis
A Parallel Approach to Perform Threshold Value Analysis and Verification of Genetic Logic Circuit Models
Role: MS Thesis Co-supervisor; Co-developer.
Tools and skills used: LabVIEW.
In this work a parallel implementation of the threshold value analysis algorithm (in DVASim) has been proposed which produces the results faster by up to 16 times.
The algorithm was further improved for consistent runtimes across multiple simulation runs under the same parameter settings, reducing the worst-case standard deviation in runtime from 6.637 to 1.841. New algorithm also estimates the threshold value more accurately.